1. Field of the Invention
The present invention relates to a self-bootstrapping device, and more particularly to a self-bootstrapping device for sufficiently bootstrapping a bias applied to the gate of a MOS transistor included in the decoder of a semiconductor memory device requiring a high integration degree so that the MOS transistor can transmit the potential from its drain to its source.
2. Description of the Prior Art
Conventionally, self-bootstrapping devices have been used as decoders for decoding word lines of semiconductor memory devices in order to increase the integration of such semiconductor devices. Such self-bootstrapping devices also serve to boost an operating voltage to a level higher than the source voltage, thereby enabling word lines of memory devices to be effectively decoded.
NMOS transistors included in semiconductor memory devices, which may be those adapted to decode word lines or those included in pull-up drivers of data out buffers and coupled to the source voltage, need a gate potential higher than the sum of a drain potential and a threshold voltage.
In this connection, a scheme has been proposed, which uses a level shifter for boosting the potential at a particular node to a level considerably higher than the source voltage. This method is illustrated in FIG. 1 in which the level shifter is denoted by the reference numeral 10. The level shifter 10 serves to boost the output from an address decoder circuit 20. A boosted signal from the level shifter 10 is applied to the gate of an NMOS transistor Q1. In this case, the boosted voltage Vpp output from the level shifter 10 should be higher than the maximum potential at the source or drain of the NMOS transistor Q1, namely, the source voltage Vcc by a value corresponding to the threshold voltage. In this case, however, it is required to use a separate voltage supply source. Since the high level source voltage should be used at highly dense regions in this case, it may adversely affect the memory device. For example, the stability of the memory device may be degraded.
In order to solve such problems, another scheme has been proposed, wherein a self-bootstrapping device is used. In this case, two NMOS transistors are used, on of which serves to perform a signal transmission. To the gate of the signal transmission NMOS transistor, the other NMOS transistor is coupled at its drain. With such a construction, the signal transmission NMOS transistor has a gate voltage self-bootstrapped in accordance with a variation in its drain voltage.
Such a self-bootstrapping device is illustrated in FIG. 2. In this self-bootstrapping device, the signal transmission NMOS transistor, which may be that of FIG. 1, is supplied at its gate with the drain voltage of the other NMOS transistor in place of an externally input particular voltage. In FIG. 2, the NMOS transistor requiring the bootstrap is the transistor Q2. The other NMOS transistor Q3 is coupled at its source to the gate of the NMOS transistor Q2. The NMOS transistor Q3 is also coupled to an address decoder circuit 20. A gate capacitor C1 for the NMOS transistor Q2 is formed between the source and gate of the NMOS transistor Q2. A gate overlap capacitor C2 is also formed between the gates of the NMOS transistors Q2 and Q3. A junction capacitor C3 is also formed because both the gate of the NMOS transistor Q2 and the source of the NMOS transistor Q3 have N' diffusion regions formed in a P' substrate, respectively.
FIG. 3A illustrates the layout of a bootstrapping transistor used in conventional self-bootstrapping devices. FIG. 3B is a cross-sectional view taken along the line A--A' of FIG. 3A. This transistor includes a pair of n.sup.+ diffusion regions formed at desired portions of a semiconductor substrate and spaced apart from each other by a desired distance, and a gate electrode formed over the substrate between the n.sup.+ diffusion regions.
The operation of the self-bootstrapping device having the above-mentioned construction will now be described in conjunction with FIG. 2. When the address decoder circuit 20 operates in response to an address input signal Ai applied thereto, it outputs a signal having a level corresponding to the source voltage Vcc. As a result, the NMOS transistor Q2 is applied at its gate with a voltage corresponding to the difference between the source voltage Vcc and the threshold voltage Vth. When the drain potential of the NMOS transistor Q2 increases up to an optional voltage Vx less than the voltage difference between Vcc and Vth, the gate potential of the NMOS transistor Q2 is self-bootstrapped by the capacitor C1 formed between the gate and source of the transistor Q2. As a result, the source potential of the NMOS transistor Q2 increases. At this time, the NMOS transistor turns off because the potential difference between its gate and source becomes lower than the threshold voltage.
In this case, the level of the self-bootstrapped voltage is determined by the co-relationship among the gate overlap capacitor C2, the junction capacitor C3 and the gate capacitor C1 of NMOS transistor Q2. In other words, the self-bootstrapped voltage level is proportional to the value of C1/(C1+C2+C3).
On the other hand, the NMOS transistor Q2 has a compact size when it is used in highly densely integrated semiconductor memory devices. In this case, however, the NMOS transistor Q3 is difficult to be compact in proportion to the compactness of the NMOS transistor Q2 due to various reasons involved in the fabrication thereof. As a result, the junction capacitor C3 has a relatively increased capacitance, as compared to the capacitor C1. This results in a decrease in the value of C1/(C1+C2+C3), thereby dropping the bootstrapped voltage level of the NMOS transistor Q2.